MMIO Bridge & Systolic Accelerator

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01 // HOST REGISTER INTERFACE 02 // MMIO CONTROL BRIDGE 03 // SYSTOLIC ACCELERATOR REG_OPCODE [0x01] REG_DIM [8x8] REG_SRC_ADR [0x1000] REG_DST_ADR [0x2000] REG_STATUS [DONE=0] STATE_IDLE STATE_LOAD_INPUTS STATE_COMPUTE_TILE STATE_STORE_OUTPUTS STATE_COMPLETE MAPPING DETAIL: TILE [3,4] ROW A[3,:] COL B[:,4] ACCUMULATOR C C[3,4] += A[3,k] * B[k,4]