Online Softmax Across Tiled Attention
FlashAttention Memory-Efficient SRAM Pipelinining
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BASELINE PATH (QUADRATIC HBM)
FULL N×N MATRIX
Materialized in HBM
O(N²) R/W Bottleneck
AVOIDED HBM TRAFFIC
0 KB
ESTIMATED SPEEDUP
1.0x (Baseline)
SRAM COMPUTE CHAMBER (ON-CHIP)
LOAD
UPDATE
SCALE
QUERY TILE Q_i
KEY TILE K_j
VALUE TILE V_j
LOCAL MAP S_ij
RUNNING STATS
ACCUMULATOR O_i
HBM OUTPUT O
SRAM REGISTER HUD
ACTIVE TILE: TILE 1 / 2
m_i = -inf | l_i = 0.0