Apple Silicon Pipeline Visualizer
Prefix Cache: OFF
Shortlist: ON
Pause Flow
Reset
01 // INGEST & CACHE
02 // NEURAL COMPUTE
03 // PRUNING & DECISION
EST. EXECUTION LATENCY
14.2 ms
PIPELINE MODE
FULL COMPUTE
PREFIX CHK
BYPASS CACHE HIT
PROMPT
TENSORS
EMBEDS
CANDIDATES
PRUNED (TOP-K)
LOGITS
INPUT STATE
PREFIX CACHE
TOKEN & PACKING
MODERNBERT ENC
SHORTLIST FILTER
DECISION HEADS
FINAL OUTPUT
SYSTEM READY // CLICK ANY NODE FOR DETAILS
Interactive system diagram depicting token ingestion, neural execution, and prefix caching mechanisms optimized for Apple Silicon Unified Memory Architecture.