Stage 1: Single Path, Single Core
Stage 1
Stage 2
Stage 3
⏸ Pause
↺ Reset
Layer 1 // Application Interface
Layer 2 // QUIC Core State & Engine
Layer 3 // CPU Execution & Path Scheduling
Layer 4 // I/O Boundary & Feedback Network
BUFFERS
REGISTER
CC HOOKS
DISPATCH
WORKER 1
WORKER 2
SCHED B
SCHED C
INGRESS ACK
PACING/RETX
APPLICATION
EXTENSION MODULE
CONN STATE
PKT NUM SPACES
CONGESTION CTRL
CPU 0
CPU 1
CPU 2
PATH A
PATH B
PATH C
UDP SOCKETS
TIMERS
FEEDBACK LOOP
ACKS / PACING / RETX
SYSTEM COMPONENT INSPECTOR
Hover over or click any node in the diagram to inspect its role, state mappings, and data flow properties.